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Preliminary Technical Data
FEATURES
128-position End-to-end resistance 5 k, 10 k, 50 k, 100 k Ultra-Compact SC70-6 (2 mm x 2.1 mm) package I2C compatible interface Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 35 ppm/C Low power, IDD = 3 A Typical Wide operating temperature -40C to +125C Evaluation board available
128-Position I2C Compatible Digital Resistor AD5246
FUNCTIONAL BLOCK DIAGRAM
VDD A I C INTERFACE W WIPER REGISTER B
2
SCL SDA
APPLICATIONS
Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment
GND
Figure 1.
PIN CONFIGURATION
1 2
VDD GND SCL
B W
6 5
GENERAL OVERVIEW
The AD5246 provides a compact 2x2.1mm packaged solution for 128 position adjustment applications. This device performs the same electronic adjustment function as a variable resistor. Available in four different end-to-end resistance values (5k, 10k, 50k, 100k ) these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. The wiper settings are controllable through the I2C compatible digital interface, which can also be used to read back the present wiper register control word. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC latch. Operating from a 2.7 to 5.5 volt power supply and consuming less than 3A allows for usage in portable battery operated applications.
3
SDA 4
Figure 2.
Note: The terms digital potentiometer, VR, and RDAC are used interchangeably.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Rev. PrF6/21/03
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD5246 TABLE OF CONTENTS
Electrical Characteristics--5 k Version ...................................... 3 Electrical Characteristics--10 k, 50 k, 100 k Versions ....... 4 Timing Characteristics--5 k, 10 k, 50 k, 100 k Versions 5 Absolute Maximum Ratings1 .......................................................... 6 I2C Interface....................................................................................... 7 Operation........................................................................................... 8 Programming the Variable Resistor ........................................... 8 I2C Compatible 2-Wire Serial Bus.............................................. 8 Level Shifting for Bidirectional Interface .................................. 9 ESD Protection ............................................................................. 9
Preliminary Technical Data
Terminal Voltage Operating Range.............................................9 Power-Up Sequence ................................................................... 10 Layout and Power Supply Bypassing ....................................... 10 Pin Configuration and Function Descriptions........................... 11 Pin Configuration ...................................................................... 11 Pin Function Descriptions ........................................................ 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 12 ESD Caution................................................................................ 12
REVISION HISTORY
Revision 0: Initial Version
Rev. PrF | Page 2 of 13
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS--5 k VERSION
(VDD = 5 V 10%, or 3 V 10%; VA = +VDD; -40C < TA < +125C; unless otherwise noted.) Table 1.
Parameter DC CHARACTERISTICS--RHEOSTAT MODE Resolution Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Wiper Resistance RESISTOR TERMINALS Voltage Range4 Capacitance5 B Capacitance5 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7 Bandwidth -3dB Total Harmonic Distortion Resistor Noise Voltage Density Symbol N R-DNL R-INL RAB RAB/T RW VB,W CB CW ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD PDISS PSS Conditions Min Typ1 Max 7 +1.5 +4 +30 120 VDD 45 60 1 2.4 0.8 VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 2.1 0.6 1 5 2.7 VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V 10%, Code = Midscale RAB = 5 k, Code = 0x40 VA = 1 V rms, VB = 0 V, f = 1 kHz RWB = 2.5 k, RS = 0 3 0.02 5.5 8 40 0.05
AD5246
Unit Bits LSB LSB % ppm/C V pF pF nA V V V V A pF V A W %/%
RWB, RWB, TA = 25C Wiper = no connect
-1.5 -4 -30
0.1 0.75 45 50
GND f = 1 MHz, measured to GND, Code = 0x40 f = 1 MHz, measured to GND, Code = 0x40 VA = VDD/2
BW_5K THDW eN_WB
1.2 0.05 6
MHz % nV/Hz
Rev. PrF | Page 3 of 13
AD5246
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS--10 k, 50 k, 100 k VERSIONS
(VDD = 5 V 10%, or 3 V 10%; VA = +VDD; -40C < TA < +125C; unless otherwise noted.) Table 2.
Parameter DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Wiper Resistance RESISTOR TERMINALS Voltage Range4 Capacitance5 B Capacitance5 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7 Bandwidth -3dB Total Harmonic Distortion Resistor Noise Voltage Density Symbol R-DNL R-INL RAB RAB/T RW VB,W CB CW ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD PDISS PSS Conditions RWB, VA = no connect RWB, VA = no connect TA = 25C Wiper = no connect VDD = 5 V Min -1 -2 -30 Typ1 0.1 0.25 45 50 GND f = 1 MHz, measured to GND, Code = 0x40 f = 1 MHz, measured to GND, Code = 0x40 VA = VDD/2 2.4 0.8 VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 2.1 0.6 1 5 2.7 VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V 10%, Code = Midscale RAB = 10 k/50 k/100 k, Code = 0x40 VA =1 V rms, f = 1 kHz, RAB = 10 k RWB = 5 k, RS = 0 3 5.5 8 40 0.05 45 60 1 Max +1 +2 +30 120 VDD Unit LSB LSB % ppm/C V pF pF nA V V V V A pF V A W %/%
0.02
BW THDW eN_WB
600/100/40 0.05 9
kHz % nV/Hz
Rev. PrF | Page 4 of 13
Preliminary Technical Data
TIMING CHARACTERISTICS--5 k, 10 k, 50 k, 100 k VERSIONS
(VDD = +5V 10%, or +3V 10%; VA = VDD; -40C < TA < +125C; unless otherwise noted.) Table 3.
Parameter Symbol Conditions I2C INTERFACE TIMING CHARACTERISTICS5, 8 (Specifications Apply to All Parts) SCL Clock Frequency fSCL tBUF Bus Free Time between STOP and START t1 tHD;STA Hold Time (Repeated START) t2 After this period, the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU;STA Setup Time for Repeated START Condition t5 tHD;DAT Data Hold Time t6 tSU;DAT Data Setup Time t7 tF Fall Time of Both SDA and SCL Signals t8 tR Rise Time of Both SDA and SCL Signals t9 tSU;STO Setup Time for STOP Condition t10 Min Typ1
AD5246
Max 400
Unit kHz s s s s s s ns ns ns s
1.3 0.6 1.3 0.6 0.6 100 300 300 0.6
50 0.9
NOTES 1 Typical specifications represent average readings at +25C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VA = VDD, Wiper (VW) = no connect. 4 Resistor terminals A and W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 7 All dynamic characteristics use VDD = 5 V. 8 See timing diagrams for locations of measured values.
Rev. PrF | Page 5 of 13
AD5246 ABSOLUTE MAXIMUM RATINGS1
(TA = +25C, unless otherwise noted.) Table 4.
Parameter VDD to GND VA, VW to GND Terminal Current, Ax-Bx, Ax-Wx, Bx-Wx Pulsed1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance2 JA: SC70-6 Value -0.3 V to +7 V VDD 20 mA 5 mA 0 V to +7 V -40C to +125C 150C -65C to +150C 300C 230C/W
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTES 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX - TA)/JA.
Rev. PrF | Page 6 of 13
Preliminary Technical Data
I2C INTERFACE
Table 5. Write Mode
S 0 1 0 1 1 1 0 W A X D6 D5 D4 D3 D2 D1 D0 Data Byte A P Slave Address Byte
AD5246
Table 6. Read Mode
S 0 1 0 1 1 1 Slave Address Byte 0 R A 0 D6 D5 D4 D3 Data Byte D2 D1 D0 A P
S = Start Condition P = Stop Condition A = Acknowledge X = Don't Care W = Write
R = Read RS = Reset wiper to Midscale 40H SD = Shutdown connects wiper to B terminal and open circuits A terminal. It does not change contents of wiper register. D6, D5, D4, D3, D2, D1, D0 = Data Bits
t8
SCL
t9
t2
t6 t2 t3 t8 t9 t4 t7 t5 t10
SDA
t1 P S S P
Figure 3. I2C Interface Detailed Timing Diagram
1 SCL SDA 0 1 0 1 1 1 0 R/W X D6 D5 D4 D3 D2 D1 D0 9 1 9 1
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
ACK BY AD5246
FRAME 2 DATA BYTE
ACK BY AD5246
STOP BY MASTER
Figure 4. Writing to the RDAC Register
1 SCL 0 1 0 1 1 1 0 R/W 0 D6 D5 D4 D3 D2 D1 D0 9 1 9
SDA
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
ACK BY AD5246
FRAME 2 RDAC REGISTER
NO ACK BY MASTER STOP BY MASTER
Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode
Rev. PrF | Page 7 of 13
AD5246 OPERATION
The AD5246 is a 128-position digitally controlled variable resistor (VR) device. An internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up.
Preliminary Technical Data
The general equation determining the digitally programmed output resistance between W and B is
RWB ( D) =
D x R AB + 2 x R W 128
(1)
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and B is available in 5 k, 10 k, 50 k, and 100 k. The final two or three digits of the part number determine the nominal resistance value, e.g., 10 k = 10; 50 k = 50. The nominal resistance (RAB) of the VR has 128 contact points accessed by the wiper terminal, plus the B terminal contact. The 7-bit data in the RDAC latch is decoded to select one of the 128 possible settings. Assume a 10 k part is used, the wiper's first connection starts at the B terminal for data 0x00. Since there is a 50 wiper contact resistance, such connection yields a minimum of 2 x 50 resistance between terminals W and B. The second connection is the first tap point, which corresponds to 178 (RWB = RAB/128+ RW = 78 + 2 x 50 ) for data 0x01. The third connection is the next tap point, representing 256 (2 x 78 + 2 x 50 ) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 (RAB + 2 x RW). Figure 6 shows a simplified diagram of the equivalent RDAC circuit.
where D is the decimal equivalent of the binary code loaded in the 7-bit RDAC register, RAB is the end-to-end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 10 k and the A terminal is open circuited, the following output resistance RWB will be set for the indicated RDAC latch codes. Table 7. Codes and Corresponding RWB Resistance
D (Dec.) 127 64 1 0 RWB () 10,100 5,100 178 100 Output State Full Scale (RAB + 2 x RW) Midscale 1 LSB Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of 100 is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Typical device to device matching is process lot dependent and may vary by up to 30%. Since the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 35 ppm/C temperature coefficient.
Ax
D6 D5 D4 D3 D2 D1 D0
RS RS
Wx
4 0 -
I2C COMPATIBLE 2-WIRE SERIAL BUS
The first byte of the AD5246 is a slave address byte (see Table 5 and Table 6). It has a 7-bit slave address and a R/W bit. The seven MSBs of the slave address are 0101110 followed by 0 for a write command or 0 to place the device in read mode. The 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 4). The following byte is the slave address byte, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the
Rev. PrF | Page 8 of 13
RDAC
2
LATCH AND RS DECODER
1
Bx
3
0
Figure 6. AD5246 Equivalent RDAC Circuit
Preliminary Technical Data
selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. On the other hand, if the R/W bit is low, the master will write to the slave device. 2. In the write mode, after acknowledgement of the slave address byte, the next byte is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Table 5). In the read mode, after acknowledgment of the slave address byte, data is received over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, where there are eight data bits followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 5). When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 4). In read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse which goes high to establish a STOP condition (see Figure 5).
VDD1 = 3.3V RP RP G SDA1 SCL1 3.3V S M1 D G S M2 D 5V RP RP
AD5246
VDD2 = 5V
SDA2 SCL2
E2PROM
AD5246
Figure 7. Level Shifting for Operation at Different Potentials
3.
ESD PROTECTION
All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 8 and Figure 9. This applies to the digital input pins SDA and SCL.
340 LOGIC
4.
VSS
Figure 8. ESD Protection of Digital Pins
B,W
VSS
Figure 9. ESD Protection of Resistor Terminals
A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing the part only once. For example, after the RDAC has acknowledged its slave address in the write mode, the RDAC output will update on each successive byte. If different instructions are needed, the write/read mode has to start again with a new slave address and data byte. Similarly, a repeated read function of the RDAC is also allowed.
TERMINAL VOLTAGE OPERATING RANGE
The AD5246 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals B and W that exceed VDD or GND will be clamped by the internal forward biased diodes (see Figure 10).
V DD
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 7 shows one of the implementations. M1 and M2 can be any N-channel signal FETs, or if VDD falls below 2.5 V, low threshold FETs such as the FDV301N.
W
B VSS
Figure 10. Maximum Terminal Voltages Set by VDD and VSS
Rev. PrF | Page 9 of 13
AD5246
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at terminals B and W (see Figure 10), it is important to power VDD/GND before applying any voltage to terminals B and W; otherwise, the diode will be forward biased such that VDD will be powered unintentionally and may affect the rest of the user's circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VB/W. The relative order of powering VB and VW, and the digital inputs is not important as long as they are powered after VDD/GND.
Preliminary Technical Data
device should be bypassed with disc or chip ceramic capacitors of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 11). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce.
V DD C3 + C1 10F 0.1 F VDD
AD5246
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the
GND
Figure 11. Power Supply Bypassing
Rev. PrF | Page 10 of 13
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS
1 2 3
AD5246
VDD GND SCL
Table 8.
B W
6 5
SDA 4
Figure 12.
Pin 1 2 3 4 5 6
Name VDD GND SCL SDA W B
Description Positive Power Supply. Digital Ground. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. W Terminal. B Terminal.
Rev. PrF | Page 11 of 13
AD5246 OUTLINE DIMENSIONS
Preliminary Technical Data
Figure 13.
6-Lead Thin Shrink Small Outline Transistor [SC70] (KS-6) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5246BKS5-R2 AD5246BKS5-RL7 AD5246BKS10-R2 AD5246BKS10-RL7 AD5246BKS50-R2 AD5246BKS50-RL7 AD5246BKS100-R2 AD5246BKS100-RL7 AD5246EVAL
1
RAB () 5k 5k 10k 10k 50k 50k 100k 100k See Note 1
Temperature -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 Evaluation Board
Package Option KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6
Branding D16 D16 D1D D1D D1C D1C D1A D1A
The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options.
The AD5246 contains 1976 transistors. Die size: 32 mil x 39 mil = 1,248 sq. mil.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03436-0-5/03(0)
Rev. PrF | Page 12 of 13
Preliminary Technical Data
NOTES
AD5246
Rev. PrF | Page 13 of 13

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